Fractal Paging
Wednesday, March 22, 2006
So I finally fixed a potentially fatal flaw with the paging subsystem. Before the bottom 4MB's were identity mapped and when a new page table was needed it was allocated from the physical memory manager and the appropriate entries were set by writing to that physical address! big problem after you receive a physical page above the 4MB mark. The new system uses the fractal mapping technique, whereby you map in the page directory into the last entry of itself, letting you address the page directory and all its page tables for the current address space in a linear fashion via the top 4MB's in the 4GB address space (see the picture below). In addition a quickMap() function is available to quickly map in a physical page into the current address space so as we may read or write to it, very useful as this page might be for another address space we are manipulating and will not be accessible via the fractal technique. The kernel is linked to run at the virtual address 0xC0001000 so we have an unused page table entry for the address 0xC0000000, which quickMap() uses to temporarily map in a physical page for access. The INVLPG instruction (only available on the 486 chips or higher) is used to flush the specific TLB entry (0xC0000000), incurring a mild performance hit. The new code is up in CVS.

The above diagram shows the typical address space layout for a process. Each process has its own unique address space, defined in the top 4MB's via the fractal paging technique. The kernel at the 3GB mark upwards is common and mapped accross all processes. Below the 3GB mark is the unique address space for the process. Below the 16MB mark is physical memory eligable for DMA operations.

The above diagram shows the typical address space layout for a process. Each process has its own unique address space, defined in the top 4MB's via the fractal paging technique. The kernel at the 3GB mark upwards is common and mapped accross all processes. Below the 3GB mark is the unique address space for the process. Below the 16MB mark is physical memory eligable for DMA operations.


